Learn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL Generation
Large-language-model register-transfer-level (RTL) generation has concentrated on how to train the model: fine-tuning, continued pre-training, and reinforcement learning from a verifier.
ProofPaper ↗
Key points
- On a bounded, formally specifiable task of generating single-error-correcting, double-error-detecting (SECDED) ECC memory wrappers, we hold the task, data, and correctness oracle fixed and vary two axes independently: the training regime (seven settings) and the output representation (four levels, from fully expanded flat Verilog to an eight-field configuration expanded by a deterministic generator).
- First, representation dominates: every representation close to raw RTL reaches a pass rate of at most 0.17, while the configuration reaches 0.83 with no training at all.
- Second, raw RTL hits a hard output-length limit: a 512-bit design requires 44,237 tokens of flat Verilog compared with just 69 tokens for the configuration.
- Inference energy also dominates amortized training energy.
Sources (1)
- [1]Learn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL GenerationarXiv (AI, ML, NLP, CV, robotics, multi-agent) · Oct 19, 06:38 AM
Large-language-model register-transfer-level (RTL) generation has concentrated on how to train the model: fine-tuning, continued pre-training, and reinforcement learning from a verifier.
On a bounded, formally specifiable task of generating single-error-correcting, double-error-detecting (SECDED) ECC memory wrappers, we hold the task, data, and correctness oracle fixed and vary two axes independently: the training regime (seven settings) and the output representation (four levels, from fully expanded flat Verilog to an eight-field configuration expanded by a deterministic generato
Extractive summary: sentences quoted from the sources.
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